1. Field of the Invention
The present invention generally relates to a frequency control system, and more particularly to a small-area, low-power and anti-power-noise frequency control system.
2. Description of Related Art
A phase-locked loop (PLL) is commonly used in electronic devices such as communication devices or computers to detect frequency or phase, or to perform frequency multiplication. A delay-locked loop (DLL), being similar to the PLL, utilizes a delay line instead of a voltage-controlled oscillator, and may be adopted to reduce clock skew in digital circuits.
A large capacitor is required to implement a filtering circuit in the conventional PLL, and thus occupies large circuit area. Moreover, the conventional PLL or DLL consumes large current and thus cannot be adapted to mobile or hand-held electronic devices. Further, the conventional PLL or DLL is liable to power noise, and therefore suffers low output accuracy.
A need has thus arisen to propose a novel frequency control system to overcome disadvantages of conventional systems, and may be adapted to mobile or hand-held electronic devices having limited resources or being liable to noise.